SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree-Reference-Cited by-同舟云学术

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree

Published:2023-07 Issue:7 Volume:70 Page:2762-2773
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Chen Yiming¹^ORCID,Yin Guodong¹^ORCID,Zhou Mufeng¹^ORCID,Tang Wenjun¹^ORCID,Yang Zekun¹,Lee Mingyen¹^ORCID,Du Xirui¹^ORCID,Yue Jinshan²^ORCID,Liu Jiaxin³^ORCID,Yang Huazhong¹^ORCID,Liu Yongpan¹^ORCID,Li Xueqing¹^ORCID

Affiliation:

1. Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China

2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

3. Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China

Funder

National Key Research and Development Program of China

NSFC

Beijing Nova Program

Tsinghua University–Daimler Greater China Ltd. JISM

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10164683/10102512.pdf?arnumber=10102512

Reference35 articles.

1. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

2. 15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

3. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

4. 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

5. A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array

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