Design of High Hardware Efficiency Approximate Floating-Point FFT Processor
Author:
Affiliation:
1. College of Electronics and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China
2. Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada
Funder
National Natural Science Foundation of China
Natural Science Foundation of Jiangsu Province
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10296081/10203014.pdf?arnumber=10203014
Reference32 articles.
1. Performance analysis of 8-point FFT using approximate radix-8 booth multiplier;reddy;Proc 3rd Int Conf Commun Electron Syst (ICCES),2018
2. Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements
3. A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture
4. VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications
5. DFT-based Channel Estimation Techniques for Massive MIMO Systems
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