Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s42835-019-00168-z.pdf
Reference10 articles.
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2. Manuel BR, Konguvel E, Kannan M (2017) An area efficient high speed optimized FFT algorithm. Signal Processing, Communication and Networking (ICSCN), 2017 Fourth International Conference on IEEE
3. Venkatachalam S, Ko S-B (2017) Design of power and area efficient approximate multipliers. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(5):1782–1786
4. Lin C-H, Lin C (2013) High accuracy approximate multiplier with error correction. In: Proc. IEEE 31st Int. Conf. Comput. Design, pp 33–38
5. Bansal Y, Madhu C (2016) A novel high-speed approach for 16–16 vedic multiplication with compressor adders. Comput Elect Eng 49:39–49
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