A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders-Reference-Cited by-同舟云学术

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A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders

Published:2016-01 Issue: Volume:49 Page:39-49
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Bansal Yogita,Madhu Charu

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference15 articles.

1. High-speed signed multiplier for digital signal processing applications;Saokar,2012

2. Low power ALU design by ancient mathematics;Kumar,2010

3. A high-speed block convolution using ancient indian Vedic mathematics;Hanumantharaju,2007

4. Performance evaluation of FFT processor using conventional and Vedic algorithm;Prakash,2013

5. ASIC design of a high-speed low power circuit for factorial calculation using ancient Vedic mathematics;Saha;Microelectron J,2011

Cited by 26 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Systematic exploration of N-bit Vedic multipliers: A roadmap of technological approaches in pursuit of future trends;Nano Communication Networks;2024-12

2. A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications;Scientific Reports;2023-12-16

3. An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder;International Journal of Electronics;2023-11-06

4. Implementation of Efficient Vedic Multiplier and Its Performance Evaluation;Journal of Circuits, Systems and Computers;2023-09-07

5. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders;Engineering, Technology & Applied Science Research;2023-06-02

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