An All-Digital, 1.92–7.32 mV/LSB, 0.5–2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System
Author:
Affiliation:
1. School of Electronic Science and Engineering, Southeast University, Nanjing, China
2. School of Integrated Circuit, Southeast University, Nanjing, China
Funder
National Key Research and Development Program of China
National Natural Science Foundation of China
Natural Science Foundation of Jiangsu Province
Fundamental Research Funds for the Central Universities
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10363413/10229936.pdf?arnumber=10229936
Reference33 articles.
1. Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization
2. Run-Time Protection of Multi-Core Processors From Power-Noise Denial-of-Service Attacks
3. Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
4. 25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density
5. An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
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1. 14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
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