25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9046640/9062887/09063018.pdf?arnumber=9063018
Cited by 35 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. A Transient Response Improved Digital LDO with an Approximate CEAG Analog-to-Frequency Domain Converter;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A Bandwidth-Boosted Hybrid LDO With Spike-To-Time Converter for Near-Threshold Regulation;IEEE Transactions on Power Electronics;2024-03
4. 14.6 A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
5. Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01
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