Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion-Reference-Cited by-同舟云学术

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Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion

Published:2023-12 Issue:12 Volume:70 Page:5110-5123
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Meng Xi¹^ORCID,Li Haoran¹,Chen Peng²^ORCID,Yin Jun¹^ORCID,Mak Pui-In¹^ORCID,Martins Rui P.¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China

2. State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China

Funder

Science and Technology Development Fund, Macau, SAR

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10363413/10253950.pdf?arnumber=10253950

Reference53 articles.

1. Low-Jitter Frequency Generation Techniques for 5G Communication: A tutorial

2. A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

3. A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24–30-GHz Sliding-IF 5G Transceivers

4. Flicker noise upconversion mechanisms in K-band CMOS VCOs

5. A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects

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