Low-Jitter Frequency Generation Techniques for 5G Communication: A tutorial
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4563670/9620728/09620737.pdf?arnumber=9620737
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Quantization-Robust On-Chip Jitter Measurement Technique for Multiple Local Oscillator Systems;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm2;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02
4. A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-$N$ Digital PLLs;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
5. Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
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