A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks-Reference-Cited by-同舟云学术

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks

Author:

Huang Mingqiang¹^ORCID,Liu Yucen²^ORCID,Man Changhai²^ORCID,Li Kai²^ORCID,Cheng Quan³^ORCID,Mao Wei²^ORCID,Yu Hao²^ORCID

Affiliation:

1. Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China

2. School of Microelectronics, Southern University of Science and Technology, Shenzhen, China

3. Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan

Funder

National Natural Science Foundation of China

Innovative Team Program of Education Department of Guangdong Province

Key-Area Research and Development Program of Guangdong Province

Shenzhen Science and Technology Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

Reference42 articles.

5. Systolic arrays for VLSI sparse matrix proc;kung;Proc Sparse Matrix Conf,1978

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