A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9763566/09696202.pdf?arnumber=9696202
Reference21 articles.
1. An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface
2. Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces
3. A 38 mW 40 Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28 nm CMOS for high-speed memory interface;cho;IEEE ISSCC Dig Tech Papers,2017
4. A 3-bit/2UI 27 Gb/s PAM-3 single-ended transceiver using one-tap DFE for next-generation memory interface;park;IEEE ISSCC Dig Tech Papers,2019
5. A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
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1. A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques;IEEE Journal of Solid-State Circuits;2024-08
2. A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for $4\times 24$ Gb/s/Pin Single-Ended DRAM Interface;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
3. A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
4. A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces;IEEE Journal of Solid-State Circuits;2023-08
5. A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces;IEEE Journal of Solid-State Circuits;2022
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