3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS-Reference-Cited by-同舟云学术

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3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS

Published:2020-08 Issue:8 Volume:67 Page:2647-2658
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Yoon Jong-Hyeok^ORCID,Kwon Kyeongha^ORCID,Bae Hyeon-Min^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9149959/09040875.pdf?arnumber=9040875

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR;IEEE Journal of Solid-State Circuits;2024-02

2. INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS;2023 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2023-10-27

3. Proximity Wireless Communication Technologies: An Overview and Design Guidelines;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-11

4. A 2.5–32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-06

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