Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs
Author:
Affiliation:
1. Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA
Funder
National Science Foundation
Jariet Technologies Inc
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
https://ieeexplore.ieee.org/ielam/8919/9929246/9845677-aam.pdf
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis of Random Clock Jitter Effect in Time-Interleaved DACs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
3. A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
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