A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration-Reference-Cited by-同舟云学术

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A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration

Published:2023-02 Issue:2 Volume:31 Page:199-209
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Fu Yushen¹^ORCID,Huang Chengyu¹,Sun Limeng¹,Meng Weiguang¹,Li Xueqing¹^ORCID,Yang Huazhong¹^ORCID

Affiliation:

1. Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China

Funder

NSFC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10019332/10004841.pdf?arnumber=10004841

Reference41 articles.

1. A 16b 12 GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving

2. A 16b 6 GS/S Nyquist DAC with IMD

3. A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz

4. Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM

5. A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET

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