A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier
Author:
Funder
NSF
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
https://ieeexplore.ieee.org/ielam/8919/9240118/9139258-aam.pdf
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01
2. A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration;Microelectronics Journal;2022-12
3. A 14-bit 5MS/s SAR ADC with digital calibration algorithm for OLED display touch system;Microelectronics Journal;2022-09
4. A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
5. A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS;Circuits, Systems, and Signal Processing;2021-01-21
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