A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme
Author:
Affiliation:
1. AI Institute, Shanghai Jiao Tong University,MoE Key Lab of Artificial Intelligence,Shanghai,China
2. Shanghai Jiao Tong University,Center for Analog/RF Integrated Circuit (CARFIC),Department of Micro-Nano Electronics,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937630.pdf?arnumber=9937630
Reference9 articles.
1. A 2-Then-1 Bit/Cycle Asynchronous SAR ADC with Background Offset Calibration
2. A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
3. A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration
4. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
5. A 7 bit 800MS/S SAR ADC with background offset calibration
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