A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS
Author:
Funder
JST ACCEL, Japan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9325891/09272691.pdf?arnumber=9272691
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3. Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
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