A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran
Funder
Babol Noshirvani University of Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9745276/09678975.pdf?arnumber=9678975
Reference25 articles.
1. Characterization of Half-Select Free Write Assist 9T SRAM Cell
2. Half-select disturb-free single-ended 9-transistor SRAM cell with bit-interleaving scheme in TMDFET technology
3. One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation
4. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
5. An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs
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