An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface-Reference-Cited by-同舟云学术

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An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface

Published:2000 Issue:8 Volume:47 Page:771-775
ISSN:1057-7130
Container-title:IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Noda H.,Aoki M.,Tanaka H.,Nagashima O.,Aoki H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/82/18677/00861409.pdf?arnumber=861409

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