A power efficient digitally programmable delay element for low power VLSI applications-Reference-Cited by-同舟云学术

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A power efficient digitally programmable delay element for low power VLSI applications

Published:2009-07 Issue: Volume: Page:
ISSN:
Container-title:2009 1st Asia Symposium on Quality Electronic Design
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Author:

Kobenge Sekedi Bomeh,Yang Huazhong

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5190881/5206227/05206292.pdf?arnumber=5206292

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element;Integration;2024-05

2. Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application;Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials;2021-07-13

3. A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time;Circuits, Systems, and Signal Processing;2020-09-20

4. A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment;2019 32nd IEEE International System-on-Chip Conference (SOCC);2019-09

5. A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output;Computational Advancement in Communication Circuits and Systems;2019-07-26

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