Author:
Bhattacharjee Pritam,Majumder Alak
Reference17 articles.
1. M.G. Johnson, E.L. Hudson, A variable delay line PLL for CPU-coprocessor synchronization. IEEE J. Solid-State Circ. 23(5), 1218–1223 (1988)
2. P. Gupta, A. Patra, Hybrid mode-switched controls of DC-DC boost converter circuits. IEEE Trans. Circ. Syst. II Express Briefs 52(11), 734–738 (2005)
3. J.S. Chiang, K.Y. Chen, The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock. IEEE Trans. Circ. Syst. II: Analog Digit. Sig. Process. 46(7), 945–950 (1999)
4. H. Noda, M. Aoki, H. Tanaka, O. Nagashima, H. Aoki, An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interfaces. IEEE Trans. Circ. Syst. II: Analog Digit. Signal Processing 47(8), 771–775 (2000)
5. E. Burlingame, R. Spencer An analog CMOS high-speed continuous-time FIR filter, in Solid-State Circuits Conference, 2000, ESSCIRC’00, Proceedings of the 26rd European (pp. 288–291). IEEE (2000, September)