Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Author:

Matsutani H.,Koibuchi M.,Yamada Y.,Hsu D.F.,Amano H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Dynamical Self-Reconfigurable Mechanism for Data-Driven Cell Array;Journal of Shanghai Jiaotong University (Science);2021-06-04

2. A Case for Low-Latency Network-on-Chip using Compression Routers;2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP);2021-03

3. Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency;2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT);2017-09

4. Optimized Core-Links for Low-Latency NoCs;2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing;2015-03

5. Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips;Microprocessors and Microsystems;2015-02

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