A Case for Low-Latency Network-on-Chip using Compression Routers
Author:
Funder
University of Tokyo
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9406783/9407036/09407193.pdf?arnumber=9407193
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network;Integration;2023-03
2. A Compression Router for Low-Latency Network-on-Chip;IEICE Transactions on Information and Systems;2023-02-01
3. Boosting the Performance of Interconnection Networks by Selective Data Compression;IEICE Transactions on Information and Systems;2022-12-01
4. Distance Aware Compression for Low Latency High Bandwidth Interconnection Network;2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2022-12
5. Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression;2021 Ninth International Symposium on Computing and Networking (CANDAR);2021-11
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