A Compression Router for Low-Latency Network-on-Chip

Author:

NIWA Naoya1,SHIKAMA Yoshiya1,AMANO Hideharu1,KOIBUCHI Michihiro2

Affiliation:

1. Keio University

2. National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference19 articles.

1. [1] L.-S. Peh and W.J. Dally, “A Delay Model and Speculative Architecture for Pipelined Routers,” Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp.255-266, Jan. 2001. 10.1109/hpca.2001.903268

2. [2] W.D. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2003.

3. [3] A.R. Alameldeen and D.A. Wood, “Frequent pattern compression: A significance-based compression scheme for l2 caches,” Technical Report 1500, Computer Sciences Dept. UW-Madison, April 2004.

4. [4] F. Betzel, K. Khatamifard, H. Suresh, D.J. Lilja, J. Sartori, and U. Karpuzcu, “Approximate communication: Techniques for reducing communication bottlenecks in large-scale parallel systems,” ACM Comput. Surv., vol.51, no.1, pp.1:1-1:32, 2018. 10.1145/3145812

5. [5] M.F. Reza and P. Ampadu, “Approximate communication strategies for energy-efficient and high performance noc: Opportunities and challenges,” Great Lakes Symposium on VLSI, GLSVLSI, pp.399-404, 2019. 10.1145/3299874.3319455

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