Drop testing and finite element simulation of stacked chip scale packages with and without underfill-Reference-Cited by-同舟云学术

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Drop testing and finite element simulation of stacked chip scale packages with and without underfill

Published:2008-05 Issue: Volume: Page:
ISSN:1087-9870
Container-title:2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems
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Author:

Schneck Nathan,Johnson Zane,Schaff Chris,Bell Merideth,Stone James

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4538254/4544243/04544355.pdf?arnumber=4544355

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Finite Element Analysis of Shock & Vibration of a Printed Circuit Board Assembly Using the Beam Elements to Model the Solder Joints;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

2. Efficient multi-level modeling technique for determining effective board drop reliability of PCB assembly;Microelectronics Reliability;2013-07

3. Thermomechanical Fatigue Performance of Lead-Free Chip Scale Package Assemblies with Fast Cure and Reworkable Capillary Flow Underfills;Japanese Journal of Applied Physics;2012-05-21

4. Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling;Japanese Journal of Applied Physics;2012-04-20

5. Comparative studies on solder joint reliability of CTBGA assemblies with various adhesives using the array-based package shear test;Microelectronics Reliability;2011-09

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