Long and short covering edges in combination logic circuits-Reference-Cited by-同舟云学术

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Long and short covering edges in combination logic circuits

Published:1990 Issue:12 Volume:9 Page:1245-1253
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Li W.-N.,Reddy S.M.,Sahni S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/2289/00062769.pdf?arnumber=62769

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits;Journal of Electronic Testing;2006-04

2. Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2004-11

3. Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2003-06

4. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation;Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324);2002

5. Circuit delay calculation considering data dependent delays;Integration;1994-08

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