False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Author:

Jing-Jia Liou ,Krstic A.,Wang L.-C.,Kwang-Ting Cheng

Publisher

IEEE

Cited by 52 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits;Applied Sciences;2022-09-10

2. PLODE: Precise Logic and Delay Simulator for Structural Verilog;2021 13th International Conference on Electrical and Electronics Engineering (ELECO);2021-11-25

3. NN-SSTA: A deep neural network approach for statistical static timing analysis;Expert Systems with Applications;2020-07

4. Artificial neural network model for arrival time computation in gate level circuits;Automatika;2019-07-03

5. On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-05

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