1. Y. Taur, C.H. Wann, and D.J. Frank, “25 nm CMOS Design Considerations,” Intl. Electron Devices Meeting (IEDM), 1998, pp. 789–792.
2. X. Tang, V. De, and J.D. Meindl, “Intrinsic MOSFET Parameters Fluctuations due to Random Dopant Placement,” IEEE Transactions on VLSI Systems, Vol. 5, pp. 369–376, 1997.
3. W.N. Li, S.M. Reddy, and S.K. Sahni, “On Path Selection in Combinational Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, pp. 56–63, 1989.
4. W.N. Li, S.M. Reddy, and S.K. Sahni, “Long and Short Covering Edges in Combinational Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, pp. 1245–1253, 1990.
5. M. Sivaraman and A.J. Strojwas, “Test Vector Generation for Parametric Path Delay Faults,” in the Proc. of Intl. Test Conference (ITC), 1995, pp. 132–138.