Author:
Chao T.-H.,Hsu Y.-C.,Ho J.-M.
Cited by
41 articles.
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1. Synthesis of Clock Networks with a Mode-Reconfigurable Topology;ACM Transactions on Design Automation of Electronic Systems;2022-03-08
2. Specialized Routing;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022
3. Clock Design and Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
4. A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-07
5. Cost-Effective Robustness in Clock Networks Using Near-Tree Structures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2015-04