Characterization of Enclosed Layout Transistors for Analog Applications on a130nm Technology
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9186570/9189892/09189903.pdf?arnumber=9189903
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Behavioral and Variability Analysis of Enclosed Layout Transistors for Radiation Hardened Analog Circuits;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09
2. TID Effect of MOSFETs in SOI BCD Process and Its Hardening Technique;IEEE Transactions on Nuclear Science;2023-08
3. TID Radiation Effects on a 0.6 μm Sigma Delta ADC Radiation-Hardened-by-Design using ELTs;2023 IEEE Aerospace Conference;2023-03-04
4. An alternative radiation hardened by layout design in a CMOS technology;2022 IEEE Latin American Electron Devices Conference (LAEDC);2022-07-04
5. Pseudo-Symmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications;IEEE Transactions on Aerospace and Electronic Systems;2022
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