4 ps Resolution Time-to-Digital Converter Implementation Utilizing LUTs-Reference-Cited by-同舟云学术

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4 ps Resolution Time-to-Digital Converter Implementation Utilizing LUTs

Published:2021-12-13 Issue: Volume: Page:
ISSN:
Container-title:2021 9th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC)
language:
Short-container-title:

Author:

Hares Khadiga¹,Atef Mohamed²,Sayed Usama³,Ramzy Safwat M.¹

Affiliation:

1. Sohag University,Faculty of Engineering,Department of Electrical Engineering,Sohag,Egypt

2. United Arab Emirates University,Department of Electrical and Communication Engineering,Al Ain,United Arab Emirates,15551

3. Assiut University,Faculty of Engineering,Department of Electrical Engineering,Assiut,Egypt

Funder

United Arab Emirates University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9691394/9691306/09691418.pdf?arnumber=9691418

Reference11 articles.

1. Recent Developments and Design Challenges of High-Performance Ring Oscillator CMOS Time-to-Digital Converters

2. Picosecond precision time‐of‐flight digital converter

3. A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix

4. FPGA Based High Resolution Time to Digital Converter

5. Area efficient vernier Time to Digital Converter(TDC) with improved resolution using identical ring oscillators on FPGA

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