Area efficient vernier Time to Digital Converter(TDC) with improved resolution using identical ring oscillators on FPGA

Author:

Mattada Mahantesh P.,Guhilot Hansraj

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 4 ps Resolution Time-to-Digital Converter Implementation Utilizing LUTs;2021 9th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC);2021-12-13

2. Performance evaluation of measured time stretching approach for event timer;2021 IEEE 9th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE);2021-11-25

3. Design of Time-to-Digital Converters for Time-Over-Threshold Measurement in Picosecond Timing Detectors;IEEE Transactions on Nuclear Science;2021-04

4. Time‐to‐digital converters—A comprehensive review;International Journal of Circuit Theory and Applications;2021-01-18

5. Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA;2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing;2014-11

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