Author:
Kamat Rajanish K.,Shinde Santosh A.,Gaikwad Pawan K.,Guhilot Hansraj
Reference27 articles.
1. Camposano, R., MacMillen, D.: Design technology for systems on a chip. In: Proceedings VLSI-SoC, Montpellier, pp. 3–7, Dec 2001
2. Farrahi, A.H., Hathaway, D.J., Wang, M., Sarrafzadeh, M.: Quality of EDA CAD tools: definitions, metrics and directions, Quality Electronic Design, 2000. ISQED 2000. In: Proceedings of the IEEE 2000 First International Symposium on Quality of Electronic Design, San Jose, pp. 395–405, 20–22 Mar 2000
3. Dudek, P., Szczepański, S., Hatfield, J.V.: A high-resolution CMOS time-to-digital converter utilizing a vernier delay line. IEEE Trans. Solid-State Circuits 35(2), 240–247 (2000)
4. Karadamoglou, K., Paschalidis, N.P., Sarris, E., et al.: An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments. IEEE J. Solid-State Circuits 39(1), 214–222 (2004)
5. Paschalidis, N.P., Stamatopoulos, N., Karadamoglou, K., et al.: A CMOS time of flight system on a chip for spacecraft instrumentation. IEEE Trans. Nucl. Sci. 49(3), 1156–1163 (2002)
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