Distributed field plate effects in split-gate trench MOSFETs
Author:
Affiliation:
1. Infineon Technologies Austria AG, Siemenstrasse 2,Villach,Austria,9500
2. Infineon Technologies AG, Am Campeon 1,Neubiberg,Germany,85579
3. University of Twente, Drienerlolaan 5,NB Enschede,The Netherlands,7522
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10094038/10094053/10094167.pdf?arnumber=10094167
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3. A TLP-based characterization method for transient gate biasing of MOS devices in high-voltage technologies;willemen;Electrical Overstress/Electrostatic Discharge Symposium Proceedings,2010
4. MOS Devices for Power Electronic Applications;baliga;28th European Solid-State Device Research Conference ESSDERC,1998
5. A review of RESURF technology
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1. Ruggedness of Silicon Power MOSFETs—Part I: Cell Structure Design Related Failure: A Review;IEEE Transactions on Electron Devices;2024-06
2. Ruggedness of Silicon Power MOSFETs–Part II: Device Design Failures and Modeling: A Review;IEEE Transactions on Electron Devices;2024-06
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