Author:
Singh Surabhi,Kaur Baljit,Kaushik B. K.,Dasgupta S.
Cited by
5 articles.
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1. Design of PnR Flow For Block Level Chip for Optimizing Leakage Power;2024 Third International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS);2024-03-14
2. Minimized Junction Leakage Current for Nanoscale Mosfet Applications;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26
3. Development of Low Leakage Current in Extreme PFET Device;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26
4. Gate replacement with PMOS stacking for leakage reduction in VLSI circuits;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2015-10-13
5. A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits;Communications in Computer and Information Science;2013