Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Author:
Affiliation:
1. National Cheng Kung University,Department of Electrical Engineering,Tainan,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9983856/9983857/09983860.pdf?arnumber=9983860
Reference18 articles.
1. Divide and conquer diagnosis for multiple defects
2. Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT)
3. Multiple-defect diagnosis for Logic Characterization Vehicles
4. Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics
5. Design reflection for optimal test-chip implementation
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1. Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors;2023 IEEE International Test Conference (ITC);2023-10-07
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