A Modified Full Adder (MFA) with an introverted unique Design for Low Power VLSI Circuit Applications
Author:
Affiliation:
1. IFET College of Engineering,Dept. of ECE,Villupuram,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9761170/9761283/09761342.pdf?arnumber=9761342
Reference15 articles.
1. A Unique Design of Hybrid Full Adder for the Application of Low Power VLSI Circuits
2. Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
3. A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder
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1. Low Power CMOS GDI Full-adder Design;2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS);2023-03-17
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