Author:
Singh Salam Surjit,Leishangthem Dolly,Shah Md. Nasiruddin,Shougaijam Biraj
Cited by
10 articles.
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1. Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model;Electronics;2024-03-29
2. Design of Multi-Bit Full Adder Using Low Power m-GDI Technique;2023 IEEE World Conference on Applied Intelligence and Computing (AIC);2023-07-29
3. Design of DADDA Multiplier Using High Performance and Low Power Full Adder;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
4. Low Power CMOS GDI Full-adder Design;2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS);2023-03-17
5. Deployment of Braun Multiplier Using Novel Adder Formulations;2023 3rd International Conference on Smart Data Intelligence (ICSMDI);2023-03