Effect of interconnect parasitic variations on circuit performance parameters-Reference-Cited by-同舟云学术

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Effect of interconnect parasitic variations on circuit performance parameters

Published:2016-10 Issue: Volume: Page:
ISSN:
Container-title:2016 International Conference on Communication and Electronics Systems (ICCES)
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Author:

Venkataiah C.,Prasad K. Satya,Prasad T. Jaya Chandra

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7879537/7889804/07889958.pdf?arnumber=7889958

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. First Principle Analysis of Borophene as an On-Chip Interconnect Material;Nano;2024-06-26

2. Optimization of CNTFET and Effect of Channel Length Scaling on CNTFET and MOSFET Threshold Voltage;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

3. Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits;ACS Nano;2024-01-04

4. Advanced Parasitic Capacitance Extraction using Active Learning;2023 20th International SoC Design Conference (ISOCC);2023-10-25

5. Machine Learning in Integrated Circuit Substrate Electrical Test (IMPACT 2023);2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT);2023-10-25

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