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Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs

  • Published:2019-05 Issue:5 Volume:38 Page:888-897
  • ISSN:0278-0070
  • Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • language:
  • Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Lee SugilORCID,Kim Daewoo,Nguyen Dong,Lee JongeunORCID

Funder

Samsung

Korea Institute of Science and Technology

Free Innovative Research Fund of UNIST

National Research Foundation of Korea

Ministry of Science, ICT and Future Planning

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11

2. Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

3. Time-Domain Multiply–Accumulate Unit;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-06

4. Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies;Electronics;2023-05-10

5. RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-03
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