Formal Verification of Arithmetic Circuits by Function Extraction

Author:

Yu Cunxi,Brown Walter,Liu Duo,Rossi Andre,Ciesielski Maciej

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

2. WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

4. Formal Verification of Divider Circuits by Hardware Reduction;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

5. Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine;Lecture Notes in Computer Science;2023

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