Formal Verification of Divider Circuits by Hardware Reduction-Reference-Cited by-同舟云学术

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Formal Verification of Divider Circuits by Hardware Reduction

Published:2023-07-03 Issue: Volume: Page:
ISSN:
Container-title:2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
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Author:

Yasin Atif¹,Su Tiankai¹,Pillement Sebastien²,Ciesielski Maciej¹

Affiliation:

1. University of Massachusetts,ECE Department,Amherst,MA,USA

2. Nantes Universite, CNRS, IETR UMR 6164,Nantes,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10192100/10192102/10192137.pdf?arnumber=10192137

Reference19 articles.

1. STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra

2. Formal Verification of Arithmetic Circuits by Function Extraction

3. Bit-level analysis of an SRT divider circuit;bryant;33rd (DAC),1996

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