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Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges

  • Published:2017-06 Issue:6 Volume:36 Page:1004-1017
  • ISSN:0278-0070
  • Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • language:
  • Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Hsu Wen-Hsuan,Kochte Michael AndreasORCID,Lee Kuen-Jong

Funder

Ministry of Science and Technology of Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs;Integration;2024-01

3. An efficient diagnostic strategy for intermittent faults in electronic circuit systems by enhancing and locating local features of faults;Measurement Science and Technology;2023-12-20

4. A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs;ACM Journal on Emerging Technologies in Computing Systems;2022-10-13

5. TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC's;2022 IEEE International Test Conference India (ITC India);2022-07-24
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