TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC's
Author:
Affiliation:
1. AMD India Pvt. Ltd.,Bengaluru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9854511/9854516/09854518.pdf?arnumber=9854518
Reference20 articles.
1. Hierarchical Test Integration Methodology for 3-D ICs
2. An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST
3. BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems
4. Fault detection and redundancy design for TSVs in 3D ICs
5. On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs;chi;IEEE Design & Test,2014
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. TSPC Trigger-Based Testing Scheme for Pre-Bond Testing and Diagnosis of TSVs;2023 2nd International Conference on Sensing, Measurement, Communication and Internet of Things Technologies (SMC-IoT);2023-12-29
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