GPU-Accelerated Simulation of Small Delay Faults

Author:

Schneider EricORCID,Kochte Michael A.,Holst Stefan,Wen Xiaoqing,Wunderlich Hans-Joachim

Funder

German Research Foundation within the Project PARSIVAL

Japan Society for the Promotion of Science (JSPS) through JSPS Grant-in-Aid for Scientific Research (B)

JSPS Grant-in-Aid for Scientific Research on Innovative Areas

JSPS Grant-in-Aid for the Promotions of Bilateral Joint Research Projects (Japan-Germany)

German Academic Exchange Service

exchange project in collaboration with the JSPS

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations;2024 IEEE European Test Symposium (ETS);2024-05-20

2. Robust Pattern Generation for Small Delay Faults Under Process Variations;2023 IEEE International Test Conference (ITC);2023-10-07

3. A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits;Applied Sciences;2022-09-10

4. Graphics Processing Unit Accelerated Small Delay Fault Simulator;Journal of Communications Technology and Electronics;2021-12

5. Logic Fault Diagnosis of Hidden Delay Defects;2020 IEEE International Test Conference (ITC);2020-11-01

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