Graphics Processing Unit Accelerated Small Delay Fault Simulator
Author:
Publisher
Pleiades Publishing Ltd
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Radiation,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1134/S106422692114014X.pdf
Reference26 articles.
1. M. H. Valavi and G. Jaberipur, “Physically unclonable functions based on small delay defects in QCA,” Semicond. Sci. Technol. 35, 035024 (2020). https://doi.org/10.1088/1361-6641/ab6bae
2. C.-Y. Chen, C.-H. Cheng, J.-L. Huang, and K. Chakrabarty, “Functional-like transition delay fault test-pattern generation using a bayesian-based circuit model,” in IEEE European Test Symposium (ETS), Tallinn, Estonia, 2020 (IEEE, 2020), pp. 1–6, https://doi.org/10.1109/ETS48528.2020.9131591
3. H. K. Lee and D. S. Ha, “HOPE: An efficient parallel fault simulator for synchronous sequential circuits,” J. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 15, 1048–1058 (1996). https://doi.org/10.1109/43.536711
4. D. B. Armstrong, “A deductive method for simulating faults in logic circuits,” IEEE Trans. Comput. C-92, 464–471 (1972). https://doi.org/10.1109/T-C.1972.223542
5. E. G. Ulrich and T. Baker, “Concurrent simulation of nearly identical digital networks,” Computer 7, 39–44 (1974). https://doi.org/10.1109/MC.1974.6323496
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