EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7794484/7805805/07805834.pdf?arnumber=7805834
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Device Aware Diagnosis for Unique Defects in STT-MRAMs;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14
2. Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs;2023 IEEE International Test Conference (ITC);2023-10-07
3. Smart Hammering: A practical method of pinhole detection in MRAM memories;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
4. LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations;IEEE Transactions on Device and Materials Reliability;2022-12
5. Radiation‐Tolerant Electronic Devices Using Wide Bandgap Semiconductors;Advanced Materials Technologies;2022-09-30
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