LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations-Reference-Cited by-同舟云学术

LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations

Published:2022-12 Issue:4 Volume:22 Page:477-487
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Taghipour Shiva¹^ORCID,Kamal Mehdi²^ORCID,Asli Rahebeh Niaraki³,Afzali-Kusha Ali¹^ORCID,Pedram Massoud⁴^ORCID

Affiliation:

1. School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran

2. School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran

3. Department of Electrical Engineering, Faculty of Engineering, University of Guilan, Rasht, Iran

4. Electrical and Computer Engineering Department, University of Southern California, Los Angeles, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/7298/9970744/09866884.pdf?arnumber=9866884

Reference43 articles.

1. Hard-to-Detect Fault Analysis in FinFET SRAMs

2. STT-MRAM Sensing: A Review

3. Test challenges in embedded STT-MRAM arrays

4. EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

5. Read disturbance issue and design techniques for nanoscale STT-MRAM

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