45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control-Reference-Cited by-同舟云学术

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45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

Published:2018-10 Issue: Volume: Page:
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Container-title:2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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Author:

Gupta Vishal,Khandelwal Saurabh,Mathew Jimson,Ottavi Marco

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8586781/8602813/08602981.pdf?arnumber=8602981

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power and Stability Optimization of High Performance SRAM Cell Using Jaya Algorithms for Low Power Drone;2024 IEEE 3rd International Conference on Electrical Power and Energy Systems (ICEPES);2024-06-21

2. Single-Ended 8T SRAM cell with high SNM and low power/energy consumption;International Journal of Electronics;2022-09-09

3. A Novel Memristor-Based SRAM Design with Improved Stability in Sub-Threshold Region;Journal of The Institution of Engineers (India): Series B;2022-08-16

4. A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation;International Journal of Electronics;2021-04-11

5. Investigation of hysteresis in hole transport layer free metal halide perovskites cells under dark conditions;Nanotechnology;2020-08-10

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