A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation
Author:
Affiliation:
1. School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China
Funder
National Natural Science Foundation of China
Fundamental Research Funds for the Central Universities
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2021.1908614
Reference13 articles.
1. A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation
2. Stable SRAM cell design for the 32 nm node and beyond
3. Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS
4. 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
5. 45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control
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