Feasibility Analysis of Chip-to-Module Channel Operating at 212 Gbps
Author:
Affiliation:
1. University of L’Aquila,L’Aquila,Italy
2. Keysight Technologies Calabasas (CA),USA
3. Samtec Corporation Columbia (SC),USA
4. Keysight Technologies Santa Rosa (CA),USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9874829/9874923/09874926.pdf?arnumber=9874926
Reference12 articles.
1. Validation and Performance Evaluation of High Speed Connector Model for Channel Design at 56 Gbps and Above
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3. Efficient Prediction of Equalization Effort and Channel Performance for PCB-Based Data Links
4. Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz
5. Backplane Channel Design Exploration at 112 Gbps Using Channel Operating Margin (COM)
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